Individual modules
A state machine, an AXI wrapper, a DSP/fixed-point block, a FIFO or buffer — the one piece you're stuck on, written and verified.
Most commonVHDL / RTL development
Complete, synthesizable VHDL/RTL to your spec — a single module or a full FPGA design, with self-checking testbenches. Every block is synthesized and simulated bit-exact against a reference model before it ships. You get clean source code you own.
entity your_module // written to your spec ghdl analyze ........ PASS ghdl elaborate ...... PASS vivado ooc synth ..... PASS sim vs golden ........ BIT-EXACT delivered ............ SOURCE + TB
What you get
Send me a spec, a datasheet, or just a clear description of the module. I turn it into working, synthesizable VHDL, check it properly, and hand you the source.
Give me the requirements; I write the VHDL — entities, architectures, the lot — done to your interface and naming.
State machines, AXI memory paths, DSP and fixed-point, FIFOs, clock-domain crossing, timing-aware code. The stuff that's easy to get subtly wrong.
Every block is synthesized and simulated bit-exact against a reference model before you get it — so it actually works, not just compiles.
What I write
Whatever VHDL your project is missing. No packages, no retainers — tell me the scope and I'll quote it.
A state machine, an AXI wrapper, a DSP/fixed-point block, a FIFO or buffer — the one piece you're stuck on, written and verified.
Most commonA full design from your spec: all the RTL modules, integrated and wired, ready to drop into your Vivado project.
Spec → working RTLSelf-checking VHDL testbenches and Python reference models, so your RTL is proven correct, not assumed.
Proof it worksHalf-written, failing, or won't-synthesize VHDL taken to clean, synthesizable, verified code.
Rescue workSend your spec or describe the module — I'll scope it and get you a quote.
How I work
I use an AI-augmented workflow to write RTL quickly — but nothing reaches you until it has passed real checks. You get the speed without the "looks right, doesn't work" risk.
VHDL written to your spec and interface, fast.
GHDL analyze + elaborate; Vivado out-of-context synthesis.
Simulated bit-exact against a reference model.
Clean, commented source plus the testbench — yours to keep.
If a module doesn't pass, you don't get it. Simple as that.
Example of my work
A complete matrix-multiply accelerator for a Zynq-7020, written from a spec in VHDL-2008: an 8×8 systolic array of 64 DSP MACs, Q1.15 fixed-point, an AXI3 memory path with ping-pong buffering, control sequencer, and an AXI4-Lite register interface.
Nine RTL modules plus six self-checking testbenches and a Python golden model. Every module synthesizes cleanly and matches the golden model bit-for-bit, on the free Vivado toolchain. This is the kind of complete, verified VHDL I deliver.
Written and verified with my AI-augmented workflow — delivered as source you own.
How it goes
Send a spec, a datasheet, or describe the module you need.
I confirm exactly what you need and give you a price up front.
Clean, synthesizable VHDL, to your interface and naming.
Synthesis plus bit-exact simulation against a reference model.
Source code and testbench, documented — yours to keep and modify.
About
I'm Mordy, an FPGA / electronics engineer. I write VHDL/RTL code for teams and individuals who need a module written or a full design built — and don't have the time, or the in-house FPGA depth, to do it themselves.
I work fast, with an AI-augmented workflow, but I don't ship anything that hasn't been synthesized and checked against a reference model. You get clean code you own — not a black box, not a slide deck. Just the VHDL you needed, done right.
Tell me what you need →FAQ
Any synthesizable VHDL: individual modules (state machines, AXI wrappers, DSP and fixed-point blocks, FIFOs and buffers), complete FPGA designs, and self-checking testbenches. VHDL-2008, mainly on AMD-Xilinx Zynq and 7-series.
Yes. You get clean, commented, synthesizable VHDL that is yours to keep, modify, and build on — plus the testbench. No black boxes, no lock-in.
Out-of-context synthesis (so it's provably synthesizable) plus simulation bit-exact against a golden reference model. If a module doesn't pass, you don't receive it.
Per project — it depends on the scope. Send me your spec or describe the module and I'll give you a fixed quote up front. No subscriptions, no retainers.
Yes. I'll take half-written, failing, or won't-synthesize VHDL and bring it to clean, synthesizable, verified code.
Get started
Send me your spec, datasheet, or a description of the module. I'll reply with the scope and a fixed quote.